The operation of a computing device, such as a web server or a smart phone, is based on integrated circuits that serve as the brains of such computing devices. Thus, integrated circuits can enable web page delivery, application usage, video game playing, media streaming, participation in electronic communications, and so forth. To do so, integrated circuits execute instructions that form computer programs. These computer programs are long and complex, and execution of such computer programs demands integrated circuits that are likewise complex.
Integrated circuits execute computer programs using transistors, which individually function as switches. A number of such switches are typically required to form even a single circuit device, and numerous circuit devices are employed to execute even the simplest of program instructions. Consequently, to handle today's long computer programs with complex instructions, modern integrated circuits can have hundreds of millions of transistors. Like any other complex machine having a multitude of interoperating parts, integrated circuits may not be manufactured correctly. An integrated circuit can have a defect that results, for example, from a fault in the foundational material, or substrate, of the integrated circuit or from a fault in the fabrication process of just a single transistor among the hundreds of millions of transistors.
To identify defective integrated circuits before incorporating them into a computing device, integrated circuits can be tested, especially during the initial design, debugging, and production processes. More specifically, after integrated circuit chips are fabricated, the integrated circuits are tested to ensure that each one will ultimately work reliably and in accordance with design specifications. Originally, integrated circuit testing was performed exclusively by external automated testing equipment (ATE). Generally, ATE provides inputs to an integrated circuit chip and receives outputs from the integrated circuit chip. The ATE then analyzes the actual received outputs with regard to correct or expected outputs.
Unfortunately, using external ATE to test an integrated circuit has become increasingly slow because a single integrated circuit chip can include hundreds of millions of transistors allocated across numerous different logical blocks. This problem is especially relevant for a system-on-a-chip (SOC), which incorporates multiple different processing functionalities on a single chip. Although the number of transistors on a chip has increased dramatically by shrinking the size of each transistor, an equivalent shrinkage in the size of input/output (I/O) pads or pins has not occurred. The size of the input/output pads for an integrated circuit chip, and therefore the number of such pads that are available for input/output signaling, are therefore more constrained by physical limitations.
Moreover, there is an increasingly greater divide separating the amount of on-chip processing capabilities provided by a given integrated circuit from the ability to move data into or out of the chip via the limited number of input/output pads. As a result, given the relatively fewer number of input/output pads available per integrated circuit chip relative to the multitude of circuit devices that are to be tested within a single SOC, external testing alone can be extraordinarily time consuming. This time consumed by external testing involves people, testing equipment, space within a fabrication or testing facility, and other manufacturing resources. The extended testing time can therefore add significant costs as well as delays to integrated circuit production.
To accommodate the divergence between the number of on-chip circuit devices and the number of available input/output pads, internal testing of integrated circuit chips has been developed. This on-chip testing is referred to as built-in self-test (BIST) technology. On-chip BIST logic is capable of applying testing algorithms on different blocks of an integrated circuit while at least largely avoiding the input/output bottleneck that would be faced by external ATE executing the same testing algorithm. However, even using BIST logic, the results of applying a testing algorithm are still reported external to the integrated circuit chip. As the number of transistors on an integrated circuit chip continues to increase and as the number of detected failures increases accordingly, the bottleneck between internal processing capabilities and access to external input/output pins has again become a problem, even with BIST technology.
In other words, with the exceedingly large number of circuit devices that are to be tested on an integrated circuit, the number of detected failures has also become exceedingly large. To properly diagnose design or other systemic flaws in an integrated circuit chip, the information characterizing such detected failures is reported external to the chip for in-depth analysis. Consequently, the reporting of testing failures remains problematic with conventional approaches to integrated circuit testing.